A new method to realize full-pipelined SHA256 based on data storage is proposed. For the full-pipelined SHA256, only A and E need to be calculated each time when the status registers of the data compressor are updated, while B-D and F-H can be obtained directly from A-C and E-G of the previous round. Since A and E will no longer be used after they have been transmitted forward for four stages, the life cycles of each stage′s A and E are both 4 clock cycles. For the traditional pipeline structure, all status registers which are used to store A-H will be updated at the same time, which hence introduce a large dynamic power. Therefore, in order to reduce the numbers of registers, and then reduce the dynamic power of registers, this paper proposes a storage scheme, which uses latches to store each stage′s A and E. When the latter stage needs to use A and E of previous stage, it selects A and E stored in the latches of previous stages using MUXs. Therefore, only the values of two sets of latches(A and E) will update per stage, which can reduce the dynamic power consumption of the circuit. In the proposed scheme, latch is used instead of flip-flop as a storage unit, and data is selected by using MUXs which are composed of transfer gates. The proposed scheme is realized and verified using a 28 nm process, the simulation results show that when compared with traditional structure, the power consumption of the pipelined SHA256 using data storage scheme is reduced by about 27.5%, and the area is reduced by about 49.2%.
Application of Electronic Technique